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very low power cmos sram 64k x 16 bit bs616lv1010 r0201-bs616lv1010 revision 2.7 oct. 2008 1 pb-free and green package materials are compliant to rohs ? features y wide v cc operation voltage : 2.4v ~ 5.5v y very low power consumption : v cc = 3.0v operation current : 25ma (max.) at 55ns 2ma (max.) at 1mhz standby current : 0.5/1.5ua (max.) at 70/85 o c v cc = 5.0v operation current : 45ma (max.) at 55ns 5ma (max.) at 1mhz standby current : 3/5ua (max.) at 70/85 o c y high speed access time : -55 55ns(max.) at v cc =2.7~5.5v -70 70ns(max.) at v cc =2.4~5.5v y automatic power down when chip is deselected y easy expansion with ce and oe options y i/o configuration x8/x16 selectable by lb and ub pin. y three state outputs and ttl compatible y fully static operation y data retention supply voltage as low as 1.5v ? description the bs616lv1010 is a high performance, very low power cmos static random access memory organized as 65,536 by 16 bits and operates form a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and ci rcuit techniques provide both high speed and low power features with maximum cmos standby current of 1.5/5ua at vcc=3/5v at 85 o c and maximum access time of 55/70ns. easy memory expansion is provided by an active low chip enable (ce) and active low output enable (oe) and three-state output drivers. the bs616lv1010 has an automatic power down feature, reducing the power consumption significant ly when chip is deselected. the bs616lv1010 is available in dice form, jedec standard 44-pin tsop ii and 48-ball bga package. ? power consumption power dissipation standby (i ccsb1 , max) operating (i cc , max) v cc =5.0v v cc =3.0v product family operating temperature v cc =5.0v v cc =3.0v 1mhz 10mhz f max. 1mhz 10mhz f max. pkg type bs616lv1010dc dice bs616lv1010ac bga-48-0608 bs616lv1010ec commercial +0 o c to +70 o c 3.0ua 0.5ua 4ma 24ma 44ma 1.5ma 14ma 24ma tsop ii-44 bs616lv1010ai bga-48-0608 bs616lv1010ei industrial -40 o c to +85 o c 5.0ua 1.5ua 5ma 25ma 45ma 2ma 15ma 25ma tsop ii-44 ? pin configurations ? block diagram brilliance semiconductor, inc. reserves the right to change products and specifications without notice. a4 a3 a2 a1 a0 ce dq0 dq1 dq2 dq3 vcc vss dq4 dq5 dq6 dq7 we a15 a14 a13 a12 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 bs616lv1010ec bs616lv1010ei 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 vss vcc dq11 dq10 dq9 dq8 nc a8 a9 a10 a11 nc g h f e d c b a 1 2 3 4 5 6 a 9 a 11 a 10 nc a 12 a 14 a 13 a 15 we d13 d5 d7 d6 nc nc a 7 vss vcc d12 d11 d4 d3 nc a 5 oe a 3 a 0 a 6 a 4 a 1 a 2 nc ub d10 d1 ce d2 d0 48-ball bga top view lb d8 d9 vss vcc d14 d15 nc nc a 8 address input buffer row decoder memory array 512 x 2048 column i/o write driver sense am p column decoder address input buffer a9 a2 a1 a0 data input buffer control dq0 . . . . . . dq15 a8 a 13 a 15 a 14 a 12 a 7 a 6 a 5 a 4 16 16 16 16 7 128 2048 512 9 a11 data output buffer a3 ce we oe ub lb v cc v ss a10 . . . . . .
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 2 ? pin descriptions name function a0-a15 address input these 16 address inputs select one of the 65,536 x 16-bit in the ram ce chip enable input ce is active low. chip enable must be active when data read form or write to the device. if chip enable is not active, the dev ice is deselected and is in standby power mode. the dq pins will be in the high impedanc e state when the device is deselected. we write enable input the write enable input is active low and c ontrols read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, dat a will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. dq0-dq15 data input/output ports there 16 bi-directional ports are used to r ead data from or write data into the ram. v cc power supply v ss ground ? truth table mode ce we oe lb ub io0~io7 io8~io15 v cc current h x x x x high z high z i ccsb , i ccsb1 chip de-selected (power down) x x x h h high z high z i ccsb , i ccsb1 l h h l x high z high z i cc output disabled l h h x l high z high z i cc l l d out d out i cc h l high z d out i cc read l h l l h d out high z i cc l l d in d in i cc h l x d in i cc write l l x l h d in x i cc notes: h means v ih ; l means v il ; x means don?t care (must be v ih or v il state)
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 3 ? absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 7.0 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ?2.0v in case of ac pulse width less than 30 ns. ? operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 2.4v ~ 5.5v industrial -40 o c to + 85 o c 2.4v ~ 5.5v ? capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 6 pf c io input/output capacitance v i/o = 0v 8 pf 1. this parameter is guaranteed and not 100% tested. ? dc electrical characteristics (t a = -40 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 2.4 -- 5.5 v v il input low voltage -0.5 (2) -- 0.8 v v ih input high voltage 2.2 -- v cc +0.3 (3) v i il input leakage current v in = 0v to v cc ce= v ih -- -- 1 ua i lo output leakage current v i/o = 0v to v cc , ce= v ih or oe = v ih -- -- 1 ua v ol output low voltage v cc = max, i ol = 2.0ma -- -- 0.4 v v oh output high voltage v cc = min, i oh = -1.0ma 2.4 -- -- v v cc =3.0v 25 i cc (5) operating power supply current ce = v il , i io = 0ma, f = f max (4) v cc =5.0v -- -- 45 ma v cc =3.0v 2 i cc1 operating power supply current ce = v il , i io = 0ma, f = 1mhz v cc =5.0v -- -- 5 ma v cc =3.0v 0.5 i ccsb standby current ? ttl ce = v ih , i io = 0ma v cc =5.0v -- -- 1.0 ma v cc =3.0v 0.02 1.5 i ccsb1 (6) standby current ? cmos ce R v cc -0.2v v in R v cc -0.2v or v in Q 0.2v v cc =5.0v -- 0.4 5.0 ua 1. typical characteristics are at t a =25 o c and not 100% tested. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc(min.). 5. i cc (max.) is 24ma/44ma at v cc =3.0v/5.0v and t a =70 o c. 6. i ccsb1(max.) is 0.5ua/3.0ua at v cc =3.0v/5.0v and t a =70 o c.
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 4 ? data retention characteristics (t a = -40 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce R v cc -0.2v v in R v cc -0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce R v cc -0.2v v in R v cc -0.2v or v in Q 0.2v -- 0.02 0.5 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. v cc =1.5v, t a =25 o c and not 100% tested. 2. t rc = read cycle time. 3. i ccdr(max.) is 0.3ua at t a =70 o c. ? low v cc data retention waveform (ce controlled) ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz , t olz , t chz , t ohz , t whz c l = 5pf+1ttl output load others c l = 30pf+1ttl 1. including jig and scope capacitance. ? key to switching waveforms waveform inputs outputs must be steady must be steady may change from ?h? to ?l? will be change from ?h? to ?l? may change from ?l? to ?h? will be change from ?l? to ?h? don?t care any change permitted change : state unknow does not apply center line is high inpedance ?off? state c l (1) 1 ttl output all input pulses 90% v cc gnd rise time: 1v/ns fall time: 1v/ns 90% v cc t r v ih v ih ce R v cc - 0.2v v dr R 1.5v ce v cc
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 5 ? ac electrical characteristics (t a = -40 o c to +85 o c) read cycle cycle time : 55ns (v cc =2.7~5.5v) cycle time : 70ns (v cc =2.4~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t rc read cycle time 55 -- -- 70 -- -- ns t av q x t aa address access time -- -- 55 -- -- 70 ns t elqv t acs chip select access time (ce) -- -- 55 -- -- 70 ns t blqv t ba data byte control access time (lb, ub) -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 30 -- -- 35 ns t elqx t clz chip select to output low z (ce) 10 -- -- 10 -- -- ns t blqx t be data byte control to output low z (lb, ub) 10 -- -- 10 -- -- ns t glqx t olz output enable to output low z 5 -- -- 5 -- -- ns t ehqz t chz chip select to output high z (ce) -- -- 30 -- -- 35 ns t bhqz t bdo data byte control to output high z (lb, ub) -- -- 30 -- -- 35 ns t ghqz t ohz output enable to output high z -- -- 25 -- -- 30 ns t av q x t oh data hold from address change 10 -- -- 10 -- -- ns ? switching waveforms (read cycle) read cycle 1 (1,2,4) t rc t oh t aa d out address t oh
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 6 read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. t oh t rc t oe t be t bdo d out ce oe address t clz (5) t chz (1 , 5) t ohz (5) t olz t aa lb, ub t b a t clz (5) t chz (5) d out lb, ub ce t b a t a cs t be t bdo
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 7 ? ac electrical characteristics (t a = -40 o c to +85 o c) write cycle cycle time : 55ns (v cc =2.7~5.5v) cycle time : 70ns (v cc =2.4~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t wc write cycle time 55 -- -- 70 -- -- ns t av w l t as address set up time 0 -- -- 0 -- -- ns t av w h t aw address valid to end of write 55 -- -- 70 -- -- ns t elwh t cw chip select to end of write (ce) 55 -- -- 70 -- -- ns t blwh t bw data byte control to end of write (lb, ub) 25 -- -- 30 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr write recovery time (ce, we) 0 -- -- 0 -- -- ns t wlqz t whz write to output high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whqx t ow end of write to output active 5 -- -- 5 -- -- ns ? switching waveforms (write cycle) write cycle 1 (1) t wc t wr1 (3) t cw (11) t wp (2) t aw t ohz (4 , 10) t as t wr2 (3) t dh t dw d in d out we lb, ub ce oe address (5) t bw
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 8 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the out put state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. 12. the change of read/write cycle must accompany with ce or address toggled. t wc t cw (11) t wp (2) t aw t whz (4 , 10) t a s t wr2 (3) t dh t dw d in d out we lb, ub ce address (5) t ow (7) (8) (8 , 9) t bw ( 12 )
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 9 ? ordering information note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be exp ected to result in significant injury or death, including life- support systems and critical medical instruments. ? package dimensions ? package d: dice a: bga-48-0608 e : t so pii - 44 bs616lv1010 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material g: green, rohs compliant p: pb free, rohs compliant tsop ii-44
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 10 package dimensions (continued) 48 mini-bga (6 x 8mm) d1 view a 1.2 max. e e1 1: controlling dimensio ns are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 e n 48 3.75 e1 d1 5.25 notes
bs616 l v 1010 r0201-bs616lv1010 revision 2.7 oct. 2008 11 ? revision history revision no. history draft date remark 2.5 add icc1 characteristic parameter jan. 13, 2006 2.6 change i-grade operation temperature range may. 25, 2006 - from ?25 o c to ?40 o c 2.7 typical value of standby current is replaced by oct. 31, 2008 maximum value in featues and description section remove ?-: normal? (leaded) pkg material in ordering information

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